A Look at DMOS Transistors

Contributed by Kevin Gibb

The DMOS transistor, while fairly common in high voltage mixed signal IC’s, is not often encountered by many CMOS IC designers. We are seeing an increased interest in IC’s for automobile control electronics, inkjet printheads, and power supplies. So we think a look at some devices that have passed through our labs might be of general interest.

DMOS transistors have been used in automobiles for more than a decade now, where their ability to sustain high drain voltages and large drive currents has proven quite useful. These attributes have not been lost on chip designers as DMOS transistors are finding new uses in inkjet printhead drivers and high voltage switched power supplies, among others.

Inkjet printheads work by ejecting small bubbles of ink through nozzles onto a print media such as paper. A metal film resistor (firing resistor in Figure 1) is typically used to heat the ink creating small vapor bubbles along its surface. This process is quite rapid, with the sudden formation of the bubble driving the remaining ink in the ink cavity then through the nozzle onto the print media.

Figure 1 Firing Resistor and Nozzle from a Kodak Printhead

This process requires lots of power, which is why these resistors are almost always driven by large DMOS transistors. Figure 2, for example, shows a pair of lateral double diffused MOS (or LDMOS) transistors used by a Hewlett Packard printhead.  The source contact is shared by two transistors, having their polysilicon gates located between the common source N⁺ contact diffusion and the two drain contacts.  A P-body diffusion lies beneath the source contact and extends about 0.6 µm laterally underneath the gates, to define the effective gate length for the transistor. This gate length is considerably shorter than the 2.5 µm long polysilicon gate. For a number of years, this ability to create a transistor with an effective gate length, shorter than the physical gate length, was an attractive feature for DMOS transistors.

The transistor, when switched off, will have quite large electric fields at the drain end of the polysilicon gate. Lifting the gate poly up over a small segment of field oxide isolation (FOX) reduces the electric field at the drain end of the gate, protecting the gate oxide from avalanche breakdown.

Figure 2 HP Printhead DMOS Transistor

Figure 3 is a scanning capacitance image taken of the transistor, which shows the N-diffusions in yellow and the P-diffusions in blue. A 3 µm deep N-well surrounds the transistor and forms the N-drift region, that connects drain contact to the transistor.  This N-well is lightly doped (about 8x10¹⁵ cm^-3) so as to support large drain bias voltages without breakdown. In this case, the N-well doping suggests a breakdown voltage of the order of 50 V.

The lightly doped N-drift regions, while giving high breakdown voltages, come at the expense of high series resistances. So very wide transistors are needed to achieve high drain currents.

Figure 3 SCM Image HP DMOS Transistors

Figure 4 shows a variation to the DMOS transistor in which the P-body is electrically connected to the source contact by a P⁺ implant. This design is used in HP’s HP8250 printhead, which predates the transistor shown in Figures 2 and 3.  Tying the P-body to the source comes from conventional CMOS transistors, whereby the P-well or P-tub is tied to V_SS (and similarly the N-tub to V_DD). Asserting a ground bias to the P-body keeps the transistor threshold voltage fixed and assures low leakage currents for the off-state transistor.

Figure 4 HP DMOS Transistor

One might be tempted to think that this was pretty much it for DMOS transistor design, but the folks at Power Integrations have some novel designs to add to the mix. They are in the business of making high voltage power conversion IC’s, and by high voltage their DMOS transistors can sustain an impressive 700 V before breakdown. These transistors are made on the same die as their BiCMOS control circuitry.

The N-drift regions have a graded doping profile that gives their high breakdown voltage, but at the expense of a high resistivity drain region (or high on-state resistance). Power Integrations’ overcomes this by adding a P-buried layer, which they describe as creating JFET conduction channels within the N-drift region.  This P-buried layer appears to accomplish two tasks, first it partially depletes the surface portion of the N-drift region yielding a higher breakdown voltage, and second, it allows for a nearly doubling of the charge in the JFET channels, lowering the on-state resistance of the transistor. The details of this are disclosed in their patent US 6,207,994.

Figure 5 Power Integrations High Voltage DMOS Transistor

But this is not the only way to make high voltage transistors, as Infineon has used deep P-diffusions to achieve high breakdown voltages (see Figure 6).  The transistors are formed in an N-epi layer having an approximately 2x10¹⁵ cm^-3 doping. Under large off-state bias conditions (the chip has a bias rating of 800 V), the N-epi is believed to be fully depleted, protecting the drain edge of the transistor gate from the high voltages.

When turned on, the channel conducts current from the source contact, through to the N-epi drain, and out through the bottom of the die.

The P-body exhibits a lobed profile indicating that the devices were fabricated as a series of N-epi growths and P-implants. Not a cheap process, but likely quite effective for making these high voltage transistors.

Figure 6 Infineon SPP02N80C3 Cool MOSTM Power Transistor

Figure 7 is a higher magnification view of the polysilicon gate, the P-type channel diffusion, and the source contact. Like the second HP DMOS transistor (Figure 4), Infineon has used both P⁺ and N⁺ source implants. The P-diffusion defines a 2 µm effective gate length for this transistor.

Figure 7 SCM Gate, Channel and Source Contact

It’s easy to become engrossed in the semiconductor industry’s relentless march to smaller geometries (45 nm node as of fall 2007) and reduced bias voltages (~ 0.8-1 V V_DD), that we sometimes forget about the other end, high voltage and high power. And perhaps one advantage here is that large voltages don’t like small geometries, so old fabs can possibly get a new life.

What Glitters in Games Isn't Just Graphics (Chips) - Volterra is doing something right with power management

contributed by Laura Tomkins

When a new game comes to market, the typical picture one sees is stores with lines out the doors, people camping outside the night before its release, and anxious teenagers waiting to get their hands on the new World of Warcraft Expansion.  What the companies see is sales, income, but most importantly profit.  The spotlight is on the consoles, the game and even the latest logic chips and graphics cards. But chugging along (and reaping the same good results) are the companies providing chips like power management. Critical to success, but not nearly quite as sexy.

The semiconductor market has been competing hard for these slots in the latest graphics cards.  But there is one company that can be seen within a lot of the latest models, Volterra Semiconductors.

Within the past year, Chipworks has torn down just about all of the latest high end graphics cards and within each card, they have noticed the Volterra Semiconductors signature.  But how is it that Volterra is winning so many sockets?

At Volterra’s first quarter earnings conference call on April 21, 2008, president and CEO, Jeffery Staszak stated that the, “bookings came in strong for the [first] quarter across all areas and as a result we are well-positioned, from a backlog standpoint, going into Q2. Our inventory increased due to strategic builds we made in anticipation of the ramp in both graphics cards.”

After receiving great demands for the newly designed power chips in Q1, Volterra took a risk of preparing for similar demands within the second quarter.  While notebooks and graphics cards are the two fastest growing markets in which they focus (they also sell power semis for servers), they decided to swing a lot of their resources into the graphics cards, which made an enormous leap in their revenue during the first and second quarters.

“Our Gen-5 products are also being well accepted in the graphics market as the powered delivery requirements continue to become more demanding for these high-performance graphic card applications. We have design wins with both AMD and NVIDIA on their enthusiast refresh graphics cards. As mentioned earlier, we received orders and shipped product in Q1 for the launch of AMD’s 3870X2 and NVIDIA’s GeForce 9800GX2 dual GPU cards,” mentions Staszak.

What is it about Volterra’s devices that are so popular? 

According the Staszak, Volterra believes that the ability to manage large swings in voltage and current demands within a small package is the main feature that is most appealing to graphics card companies, such as AMD and NVIDIA.  Volterra devices enable a lot of space savings while also, with the release of the Gen-5 products, deliver better performance than previous models. Chipworks’ teardowns have confirmed that the Volterra devices have resulted in fewer overall chips on the board by bringing a lot of functionality on chip. We have also seen that many competitive devices continue to use conventional lead frame, wire bond technology.

Each video card that Chipworks has torn down contained 6 to 7 Volterra devices.  While enabling better performance and more space, each card can hold more devices, with each one of them selling for $2 to $3. 

According to data provided by ATI Technologies, Inc. and Advanced Micro Devices (AMD), the total available market for graphics cards these days is about 263 million users.  The breakdown of this consists of 197M casual gamers, 52.6M mainstream gamers, and 13.15M enthusiast gamers.

Volterra has beaten other semiconductor companies such as Analog Devices, Maxim Integrated Products, and Texas Instruments to this slot. 

If Volterra’s predictions hold true for the upcoming quarters, then we should be seeing them skyrocket past the competition.

HP Returns to its Roots with the new HP 60 Printhead

Contributed by St.J. Dixon-Warren and Tim White

Hewlett-Packard is returning to it roots with the new HP 60 printhead, which features 2006 die marks. This printhead is fabricated using a similar manufacturing process seen by Chipworks in 2001 for the 600 dot-per-inch (dpi) HP 23 (C1823D) printer cartridge. That device was fabricated using a two metal NMOS technology, featuring ~4 µm transistor gates. The die size was 8.65 mm x 7.81 mm. The HP 60 (CC643WN) is also fabricated with a two metal process, but featuring ~3 µm gates, with a 4.18 mm x 11.49 mm die size. More importantly, HP has decided not to use their well publicized Scaleable Printing Technology to fabricate the microfluidic layers on HP 60 device, rather they have returned to the use of a palladium plated, nickel metal nozzle plate.

HP 60 Ink Nozzle and Ink Cavity – Cross Section

HP 60 Ink Nozzles – Tilt View

By contrast, the more modern HP 88 printhead, which features 2003 die markings, used lithographically defined microfluidic layers composed of an organic material (likely SU-8). It is worth noting that the HP 88 was fabricated with a 3 metal, 1µm process, featuring LDMOS power transistor driving the heater resistors. The HP 88 die size is 4.39 mm x 26.05 mm. Chipworks has completed comprehensive analysis of Scaleable Printing Technology, used by the HP 88, the HP 70 and the HPDC printheads. These printers all featured a single nozzle size, ranging from 13-18 µm in diameter.

HP 88 Ink Nozzle and Ink Cavity – Cross Section

HP 88 Ink Nozzles – Plan View

The process used to create the HP 60 is similar in many respects to that published in 1994 in the Hewlett-Packard Journal, although they have dramatically increased the number of nozzles from the 50 used by the HP Deskjet 500C to 1248 on the HP 60. Both the HP 60 and the HP 88 feature 1200 dpi print resolution. The HP 60 features two nozzle sizes, unlike the older technology. Clearly HP has taken their conventional printhead manufacturing process to a new level; while choosing not to use their advanced fully-lithographic Scaleable Printing Technology for this new printhead. With the HP60 delivering very similar specifications to the fully lithographic devices, the only reason I can think that they chose this process technology is that the end result is lower cost and is more suited to a disposable cartridge.

References

• http://www.hp.com/hpinfo/newsroom/press/2008/080228xa.html 
• http://h10010.www1.hp.com/wwpc/us/en/sm/WF06c/A10-12771-64199-69422-69422-69681-12785-12786.html 
• http://h10010.www1.hp.com/wwpc/us/en/sm/WF06c/A10-12771-64199-69422-69422-3564563-3564895-3565207.html 
• http://www.hp.com/hpinfo/newsroom/press_kits/2006/ipgconf/bg_scalableprinting.pdf 
• http://www.hpl.hp.com/hpjournal/94feb/feb94a6.pdf 
• Hewlett-Packard HP60 Tri-color Print Cartridge (Part Number CC643WN) MEMS Process Review with Supplemental TEM Analysis (MPR-0805-901)
• Hewlett-Packard – Canon Printheads Focused Technology Review (FTR-0703-801)

DRAMS Go Square!

Contributed by Kevin Gibb, Process Analyst

The DRAM business split some time ago into two camps: the stacked capacitor types (Samsung, Micron, Hynix , Elpida,, ProMos and Powerchip), and the trench capacitor makers (Nanya, Qimonda, and Inotera).  The trench capacitor seems to be a lonely business as Qimonda is a spin-off from Infineon, Nanya has been in a technology partnership with Infineon (or now Qimonda) that is called Inotera. Promos used to be a trench provider, but the link to Infineon dissolved a while ago.

The challenge for both trench and stack DRAM makers is to increase the packing density, and thus data density, whilst keeping the cell capacitance at a level that provides a voltage change that can be detected by the sense amplifiers.

The stack companies can keep increasing the stack height, and have done so, and they were the first to introduce high-k capacitor dielectrics to crank up the capacitance.  For the trench designers it’s a bit more difficult – they have done amazing things etching deep, high-aspect ratio trenches, but the deeper the trenches go, the bigger they are at the top, limiting how close together they can be.

To get around this, Infineon introduced bottle-shaped trenches a few years ago – the deep trenches are dry-etched, but then an oxide collar is formed at the top of the trench, and the trenches are enlarged by an isotropic etch (probably wet), giving a larger capacitor surface without a larger trench top.  That did for a while; Infineon/Qimonda got to the 90-nm generation with this process, but by the 1-Gb, 70-nm era this wasn’t good enough either.  

So the next thing is – square trenches!  Infineon disclosed square-shaped trenches, patterned in a checkerboard fashion, with hemispherical grained silicon (HSG) capacitor electrodes, at a 70 nm node, back in 2004 at the IEDM conference[1]. This was novel then, and still seems novel now, and we have been looking for it for the past few years.

Given their industry link-up, we would expect all three trench companies (Qimonda, Nanya, and Inotera) to have pretty similar process technologies for their DRAMs. And this might be the case.

We came close in 2005 when Nanya produced its 110 nm DDR2 SDRAM (Figure 1). The 150 nm by 190 nm large rectangular trenches are placed in the same X-Y grid as the wordlines and bitlines. The capacitor dielectric was made with a bilayer of oxide and silicon nitride.

Figure 1 Nanya 110 nm DDR2 SDRAM Cell

We have had to wait until now to find the IEDM ’04 structure, as DRAM manufacturers have only just started to release their 70 nm and smaller DRAMs to the market. Qimonda has adopted the checkerboard trench pattern for their 512 Mbit (and presumably 1 Gbit) GDDR5 SGRAMs (Figure 2).

The wafers used to make these DRAMs have been rotated 45^o so that the trench sidewalls are the (110) silicon planes, and are packed quite tightly. The Qimonda cells are about 150 nm x 150 nm, about 20% smaller than the 110 nm node cell shown in Figure 1. But the new DRAM cell is about half the size of the former, so a significant improvement in silicon utilization.

The trench sidewalls also have a lobed structure, which is due to the hemispherical grained silicon that provides a much increased surface area for the capacitor. This, along with Infineon’s disclosure of atomic layer deposited Al₂O₃ capacitor dielectric, should give a big boost to the cell’s capacitance. A bigger cell capacitance, and reduced bitline resistance are two ingredients for a fast DRAM.  And this may be part of the solution to Qimonda’s impressive 5 Gbps/pin data rate for the device.

Figure 2 Qimonda GDDR5 SGRAM Checkerboard Cell Capacitors

 These chips are currently in our lab, being taken apart and examined, as I write. So we hope to have Qimonda’s process and circuit designs revealed in the very near future.  We should have a few fascinating pictures to post in the not-too-distant future!

References
[1]  J. Amon et al. “A highly manufacturable deep trench based DRAM cell layout with a planar array device in a 70 nm technology” IEDM (2004) pp73-76

Lies, Damn Lies and Conference Proceedings

By Dr. Sinjin Dixon-Warren

Lies, Damn Lies, and Statistics…the inspiration for the title is a little cliché, and maybe even a slight exaggeration, but I have long been looking for an excuse to use that phrase in a blog. Let me start out by saying that one of the amazing things about our industry is that we are so open about our respective basic research. However, in the occasional case, what is presented at conferences is actually quite different than what ends-up in commercial production.

Recently, in our analysis of the Bosch SMG070 we read that Bosch encapsulated in the MEMS sensor in a vacuum (1, 2). Despite this published information we decided to proceed with residual gas analysis of the gases in the MEMS cavity. We found hydrogen with a pressure of 3-5 torr. Not to cast any dispersions on the good people at Bosch. This case is undoubtedly one where the data presented was based on a real and functioning device; one that was probably a pre-production or R&D version. It is however, a great demonstration that sometimes reverse engineering reveals surprising differences between what is released at a conference, and what companies ultimately deliver in their commercial products.

An intriguing question is whether the hydrogen in the cavity is intentional or is an accidental consequence of the device fabrication or cap attach process? Gases are often added to the cavity of inertial sensors to provide gas damping of the MEMS structures, for example as described in a recent Analog Devices Patent (3). Given the low molecular weight of H₂, and hence low gas viscosity, I suspect that the hydrogen does not provide much fluidic damping to the MEMS structure, and thus the few torr of H₂ gas does not significantly affect the performance of the gyro.

Bosch SMG070 MEMS Gyroscope Cavity

1) R. Neul, et al., Micromachined Gyros for Automotive Applications, IEEE Sensors Journal, 7 (2007) 302.
2) U.M. Gomez, et al., The 13^th International Conference on Solid-State Sensors, Actuators and Microsystems, IEEE (2005), 184.
(3) Geen; John A., et al., United States Patent 7,017,411.

Sony has twins, with more on the way!

contributed by Ray Fontaine, Process Analyst

In February 2008, Sony announced their initiative to launch two 5 Mp, 1.75 µm pixel generation CMOS image sensors (CIS).  We’ve done a full analysis on one and recently took a peak at the second.  The IMX024 is a 1.77 µm pixel sensor for an HD camcorder, while the IMX034 is a 1.75 µm pixel sensor for a camera phone (Figure 1).

Figure 1 – Sony 1.77 µm and 1.75 µm pixel size sensors

I’ll talk about the twins in a minute, but first it is worth mentioning the CIS pixel roadmap.  Recently we’ve seen 1.4 µm pixel CIS products announced from Aptina, OmniVision, Kodak, and Samsung.  While no official announcements have been made, companies such as STMicroelectronics have successfully demonstrated pixels at these dimensions.  In Figure 2, Sony indicates that they too have a 1.4 µm pixel system-on-chip (SoC) sensor in production.

Figure 2 – Sony 1.4 µm Pixel Production

So we can see where the innovators are going, but I would like to now talk about the waypoints on the journey to the 1.4 µm pixel.  As always, it helps to follow the money.  Designing smaller pixel sensors with increased performance is a costly endeavor.  Remember the days of building a CIS using a mature process line?   Well, there is a general correlation between pixel scaling and the need for a more advanced technology generation for production.  Naturally there is some industry aversion to investing in the 1.4 µm pixel generation until every bit of performance is milked from existing pixel designs.

That is exactly what we saw in the sensors we analyzed in 2007.  Companies such as Micron and OmniVision underwent 2 and 3 rounds of optimizing their existing pixel architectures.  These iterations were evolutionary in nature; sharing pixels, optimizing the metals for optical symmetry, thinning the dielectrics over the pixels, etc.  These iterations were pushed out to the market as same size pixel sensors with improved performance.

This brings me back to the Sony twins.  They’ve taken the design evolution approach one step further by optimizing based on end application.  Figure 3 shows the color filter array from the IMX024.  The IMX024 is a 5.6 Mp, 1.77 µm pixel CIS extracted from a Sony HDR-SR11 HD camcorder.  The conventional Bayer patterned color filter array is scrapped in favor of Sony’s ClearVid pixel architecture.  This architecture features a 45° pixel arrangement and a 1:6:1 RGB color filter array.  The increased green pixel count equates to higher sensitivity.  This novel pixel layout does require specialized image processing to interpret the captured image.

Figure 3 – Sony IMX024, ClearVid Pixel Layout

Figure 4 shows the metal 1 patterning used in the pixel array.  This clever metal 1 layout not only facilitates all of the necessary electrical connections, but also includes dummy metal patterns to provide a nearly symmetrical back end structure. 

Figure 4 – Sony IMX024, Pixel at Metal 1

While the IMX024 is optimized to handle HD video, its IMX034 sister is bred for capturing still images in a much smaller product.  Figure 5 shows the back of the SO905iCS camera phone, home of the 1.75 µm pixel twin.

Figure 5 – Sony SO905iCS Camera Phone

While the packaging for the IMX024 wasn’t worth mentioning, the IMX034 uses a fairly elaborate camera module.  A “periscope” system is used to stuff the lenses and focusing mechanism into the phone while maintaining a reasonable form factor (Figure 6).

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Figure 6 – Sony IMX034 Module

The IMX034 uses a conventional Bayer patterned RGB color filter array.  To date we have only performed a bevel analysis of the pixel array (no cross sectioning).  Figure 7 shows the orthogonal metal 1 layout including the outline of the light pipe window used over the photocathodes.  The IMX024 also used a unique light pipe structure, but that is the subject of another blog. 

We have only presented the metal 1 layout for each, but of course both sensors use their own flavor of pixel architecture.  In short, you might call them fraternal twins.  Sony has the advantage of designing sensors for their own products and as such we see a synergy between the downstream products and pixel/module designers.

 Figure 7 – IMX034 at Metal 1

In addition to Sony’s two pronged attack at the 1.75 µm pixel generation, they’ve also announced their production of a full frame CIS for DSLR applications.  This will be a first for Sony, and will be featured in their 25 Mp “Flagship” DSLR.  We wonder if the new sensor will be an evolution of their IMX021 pixel shown in Figure 8.  This was an APS-C size sensor taken from an Alpha 700.

Figure 8 – Sony IMX021 CIS from Alpha 700

Finally, putting together this blog has been interesting timing as Sony has just announced their development of a backside illumination (BSI) sensor.  Figure 9, taken from the Sony press release, shows a cross sectional view of their planned 1.75 µm BSI pixel structure.  OmniVision recently presented their OmniBSI™ architecture, while STMicroelectronics, MagnaChip, and others have also demonstrated the technology.  While this concept is not new the application should certainly prove to be disruptive and it is great to see new solutions to the shrinking pixel problem (signal-to-noise).  Sony has been one of the top innovators in the CIS game, and we look forward to a product announcement using this exciting technology.

Figure 9 – Sony Backside Illumination Sensor 

Links used:

http://www.sony.net/SonyInfo/IR/financial/fr/viewer/Semiconductor/2007/

http://www.chipworks.com/seamark.aspx?sm=s4%3BDatedfl10%3BDeviceType17%3BCMOS+Image+Sensorfl10%3BReportCode12%3BIPR-0804-801&cw=detail

http://www.sony.net/SonyInfo/News/Press/200801/08-010E/index.html

http://www.engadget.com/2008/02/01/sony-25mp-full-frame-dslr-hands-on/

http://www.sony.net/SonyInfo/News/Press/200806/08-069E/index.html

http://www.ovt.com/data/newsreleases/english/BSI%20Technology%20launch%20release_FINAL.pdf